(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to create a gate structure, for a complementary metal oxide semiconductor, (CMOS), device, comprised with a P type doped region, in a first region of the gate structure, and comprised with an N type doped region, in a second region of the gate structure.
(2) Description of the Related Art
The objective of increasing semiconductor device performance has been successfully addressed by the trend to micro-miniaturization, or the ability to fabricate semiconductor devices, using sub-micron features. However when using sub-micron features to fabricate a buried channel, P channel, or pMOS, type device, an undesirable, yield and reliability degrading, short channel effect, can result. Therefore the pMOS devices, in the CMOS cell, are now being fabricated as surface channel devices, similar to the N channel, or nMOS counterparts. However to avoid higher threshold, and operating voltages, encountered when using an N type, polysilicon gate structure, for the surface channel, pMOS device, a P doped gate structure is employed, resulting in a minimum work function, hence a lower threshold voltage. However to obtain the same threshold voltage benefits, the nMOS devices still have to be fabricated using N doped, gate structures. Thus the use of a continues dual gate structure, comprised of polysilicon, or polycide, (metal silicide-polysilicon), featuring P type doped regions, overlying subsequent pMOS channel regions, and N type doped regions, overlying subsequent nMOS channel regions, is used to traverse both the CMOS cell.
The use of polycide gate structure, improving performance as a result of lower word line resistance, can however present problems, when used as a component of a dual gate structure. The diffusion coefficient for dopants such as boron, phosphorous and arsenic, is about five orders of magnitude higher in metal silicide layers, than the diffusion coefficient for these same dopants in polysilicon. Therefore during subsequent hot process procedures, such as source/drain activation anneals, or the formation of self-aligned contact openings, and structures, dopants in the polysilicon component of the polycide gate structure, can enter the metal silicide component of the polycide gate structure, then quickly move laterally in the metal silicide, and perhaps diffuse into an underlying region of the polysilicon component, that has been doped with a dopant of the opposite type. This auto-doping phenomena can result in unwanted threshold voltages, for the subsequent CMOS devices.
This present invention will describe a process for forming a polycide, dual gate structure, however this invention will feature the use of an undoped polysilicon layer, placed between the underlying, dual doped, polysilicon component, and the overlying metal silicide layer. Therefore during subsequent process steps, performed at elevated temperatures, only slow, or no movement of dopants, into the undoped polysilicon layer occurs, avoiding the auto-doping phenomena, and thus allowing the designed and desired operating and threshold voltages, to be maintained. Prior art, such as Fujii et al, in U.S. Pat. No. 5,341,041, as well as Matsumoto in U.S. Pat. No. 5,877,535, describe processes for reducing auto-doping, in a dual gate structure, via use of pre-doping of the metal silicide component. However these prior arts do not describe the novel approach of using an undoped polysilicon layer, used to prevent dopants from the polysilicon component of a polycide, dual gate structure, from reaching the metal silicide component of the polycide structure, where it can initiate the unwanted auto-doping phenomena.